CLO=0, SDAI=0, IICRST=0, SCLO=0, ICE=0, SOWP=0, SCLI=0, SDAO=0
I2C Bus Control Register 1
SDAI | SDA Line Monitor 0 (0): SDAn line is low 1 (1): SDAn line is high |
SCLI | SCL Line Monitor 0 (0): SCLn line is low 1 (1): SCLn line is high |
SDAO | SDA Output Control/Monitor 0 (0): Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low 1 (1): Read: IIC releases SDAn pin Write: IIC releases SDAn pin |
SCLO | SCL Output Control/Monitor 0 (0): Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low 1 (1): Read: IIC releases SCLn pin Write: IIC releases SCLn pin |
SOWP | SCLO/SDAO Write Protect 0 (0): Write enable SCLO and SDAO bits 1 (1): Write protect SCLO and SDAO bits |
CLO | Extra SCL Clock Cycle Output 0 (0): Do not output extra SCL clock cycle (default) 1 (1): Output extra SCL clock cycle |
IICRST | I2C Bus Interface Internal Reset 0 (0): Release IIC reset or internal reset 1 (1): Initiate IIC reset or internal reset |
ICE | I2C Bus Interface Enable 0 (0): Disable (SCLn and SDAn pins in inactive state) 1 (1): Enable (SCLn and SDAn pins in active state) |